Projects

RISC-67 — 2-Way Superscalar Out-of-Order CPU

An out-of-order RV32IM processor in SystemVerilog, built with Albert Jiang and Taowei Huang for ECE 411. Explicit register renaming, per-unit reservation stations, a split load/store queue, and a gshare branch predictor.

645 MHz max clock frequency
~200K synthesized area
0.508 IPC on CoreMark
0.495 geometric-mean IPC across the six benchmarks

High-level block diagram of the RISC-67 out-of-order pipeline

For more info, here is the full report.

OStritch — A RISC-V OS Kernel

Key features:

Page virtual memory protection
Multiple user processes with preemptive thread switching in user space
Expandable file system based on ext2
VirtIO block device driver
Can load and execute any ELF file
VGA display driver
User programs: POSIX-like shell, Snake game

Why "OStritch"? During development, we encountered a quirky bug: increasing the timer speed for preemptive interrupts caused random unexpected crashes. Our initial solution was to implement the "Ostrich Algorithm" which solved the problem immediately. We realized the bug was due to a locking issue on kernel bootup :)

Plants vs Zuofu

Recreation of Plants vs Zombies primarily using SystemVerilog, deployed on the Spartan 7 FPGA.